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| - 1 - 256mb ddr sdram rev. 0.4 may. 2002 ? double-data-rate architecture; two data transfers per clock cycle ? bidirectional data strobe(dqs) ? four banks operation ? differential clock inputs(ck and ck ) ? dll aligns dq and dqs transition with ck transition ? mrs cycle with address key programs -. read latency 2, 2.5 (clock) -. burst length (2, 4, 8) -. burst type (sequential & interleave) ? all inputs except data & dm are sampled at the positive going edge of the system clock(ck) ? data i/o transactions on both edges of data strobe ? edge aligned data output, center aligned data input ? ldm,udm/dm for write masking only ? auto & self refresh ? 7.8us refresh interval(8k/64ms refresh) ? maximum burst refresh cycle : 8 ? 66pin tsop ii package key features operating frequencies *cl : cas latency - b3(ddr333) - a2(ddr266a) - b0(ddr266b) - a0(ddr200) speed @cl2 133mhz 133mhz 100mhz 100mhz speed @cl2.5 166mhz 133mhz 133mhz - part no. org. max freq. interface package k4h560438d-tc/lb3 64m x 4 b3(ddr333@cl=2.5) sstl2 66pin tsop ii k4h560438d-tc/la2 a2(ddr266@cl=2) k4h560438d-tc/lb0 b0(ddr266@cl=2.5) k4h560438d-tc/la0 a0(ddr200@cl=2) k4h560838d-tc/lb3 32m x 8 b3(ddr333@cl=2.5) sstl2 66pin tsop ii k4h560838d-tc/la2 a2(ddr266@cl=2) k4h560838d-tc/lb0 b0(ddr266@cl=2.5) k4h560838d-tc/la0 a0(ddr200@cl=2) k4h561638d-tc/lb3 16m x 16 b3(ddr333@cl=2.5) sstl2 66pin tsop ii k4h561638d-tc/la2 a2(ddr266@cl=2) k4h561638d-tc/lb0 b0(ddr266@cl=2.5) k4h561638d-tc/la0 a0(ddr200@cl=2) ordering information
- 2 - 256mb ddr sdram rev. 0.4 may. 2002 package pinout & dimension dm is internally loaded to match dq and dqs identically. 256mb package pinout column address configuration v dd 1 66 pin tsop(ii) (400mil x 875mil) dq 0 2 v ddq 3 nc 4 dq 1 5 v ssq 6 nc 7 dq 2 8 v ddq 9 nc 10 dq 3 11 v ssq 12 ba 0 20 cs 19 ras 18 cas 17 we 16 nc 15 v ddq 14 nc 13 v dd 27 a 3 26 a 2 25 a 1 24 a 0 23 ap/a 10 22 ba 1 21 v ss 54 dq 7 53 v ssq 52 nc 51 dq 6 50 v ddq 49 nc 48 dq 5 47 v ssq 46 nc 45 dq 4 44 v ddq 43 a 11 35 36 cke 37 ck 38 dm 39 v ref 40 v ssq 41 nc 42 v ss 55 a 4 56 a 5 57 a 6 58 a 7 59 a 8 60 a 9 34 (0.65 mm pin pitch) 33 32 31 30 29 28 61 62 63 64 65 66 nc nc nc nc nc v dd nc dqs nc v ss ck nc a 12 64mb x 4 32mb x 8 16mb x 16 v ss nc v ssq nc dq 3 v ddq nc nc v ssq nc dq 2 v ddq a 11 cke ck dm v ref v ssq nc v ss a 4 a 5 a 6 a 7 a 8 a 9 nc dqs nc v ss ck nc a 12 v ss dq 15 v ssq dq 14 dq 13 v ddq dq 12 dq 11 v ssq dq 10 dq 9 v ddq a 11 cke ck udm v ref v ssq dq 8 v ss a 4 a 5 a 6 a 7 a 8 a 9 nc udqs nc v ss ck nc a 12 v dd nc v ddq nc dq 0 v ssq nc nc v ddq nc dq 1 v ssq ba 0 cs ras cas we nc v ddq nc v dd a 3 a 2 a 1 a 0 ap/a 10 ba 1 nc nc nc nc nc v dd v dd dq 0 v ddq dq 1 dq 2 v ssq dq 3 dq 4 v ddq dq 5 dq 6 v ssq ba 0 cs ras cas we ldm v ddq dq 7 v dd a 3 a 2 a 1 a 0 ap/a 10 ba 1 nc ldqs nc nc nc v dd bank address ba0-ba1 row address a0-a12 auto precharge a10 ms-024fc organization column address 64mx4 a0-a9, a11 32mx8 a0-a9 16mx16 a0-a8 - 3 - 256mb ddr sdram rev. 0.4 may. 2002 bank select timing register a d d r e s s r e g i s t e r r e f r e s h c o u n t e r r o w b u f f e r r o w d e c o d e r c o l . b u f f e r data input register serial to parallel 8mx8 8mx8 8mx8 8mx8 s e n s e a m p 2 - b i t p r e f e t c h o u t p u t b u f f e r i / o c o n t r o l column decoder latency & burst length programming register d l l s t r o b e g e n . ck, ck add lcke ck, ck cke cs ras cas we dm dm ck, ck lcas lras lcbr lwe lwcbr l r a s l c b r ck, ck 8 8 4 4 we dm x4 dqi data strobe block diagram (16mbit x 4 i/o x 4 banks) - 4 - 256mb ddr sdram rev. 0.4 may. 2002 bank select timing register a d d r e s s r e g i s t e r r e f r e s h c o u n t e r r o w b u f f e r r o w d e c o d e r c o l . b u f f e r data input register serial to parallel 4mx16 4mx16 4mx16 4mx16 s e n s e a m p 2 - b i t p r e f e t c h o u t p u t b u f f e r i / o c o n t r o l column decoder latency & burst length programming register d l l s t r o b e g e n . ck, ck add lcke ck, ck cke cs ras cas we dm dm ck, ck lcas lras lcbr lwe lwcbr l r a s l c b r ck, ck 16 16 8 8 we dm x8 dqi data strobe block diagram (8mbit x 8 i/o x 4 banks) - 5 - 256mb ddr sdram rev. 0.4 may. 2002 bank select timing register a d d r e s s r e g i s t e r r e f r e s h c o u n t e r r o w b u f f e r r o w d e c o d e r c o l . b u f f e r data input register serial to parallel 2mx32 2mx32 2mx32 2mx32 s e n s e a m p 2 - b i t p r e f e t c h o u t p u t b u f f e r i / o c o n t r o l column decoder latency & burst length programming register d l l s t r o b e g e n . add lcke ck, ck cke cs ras cas we l(u)dm ldm ck, ck lcas lras lcbr lwe lwcbr l r a s l c b r ck, ck 32 32 16 16 lwe ldm x16 dqi data strobe block diagram (4mbit x 16 i/o x 4 banks) - 6 - 256mb ddr sdram rev. 0.4 may. 2002 input/output function description symbol type description ck, ck input clock : ck and ck are differential clock inputs. all address and control input signals are sam- pled on the positive edge of ck and negative edge of ck . output (read) data is referenced to both edges of ck. internal clock signals are derived from ck/ ck . cke input clock enable : cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for all functions except for disabling outputs, which is achieved asynchronously. input buffers, excluding ck, ck and cke are disabled during power-down and self refresh modes, providing low standby power. cke will recognize an lvcmos low level prior to vref being stable on power-up. cs input chip select : cs enables(registered low) and disables(registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ras , cas , we input command inputs : ras , cas and we (along with cs ) define the command being entered. ldm,(u)dm input input data mask : dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. dm pins include dummy loading internally, to matches the dq and dqs load- ing. for the x16, ldm corresponds to the data on dq0-dq7 ; udm correspons to the data on dq8-dq15. ba0, ba1 input bank addres inputs : ba0 and ba1 define to which bank an active, read, write or pre- charge command is being applied. a [n : 0] input address inputs : provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op-code during a mode register set command. ba0 and ba1 define which mode register is loaded during the mode register set command (mrs or emrs). dq i/o data input/output : data bus ldqs,(u)dqs i/o data strobe : output with read data, input with write data. edge-aligned with read data, cen- tered in write data. used to capture write data. for the x16, ldqs corresponds to the data on dq0-dq7 ; udqs corresponds to the data on dq8-dq15. nc - no connect : no internal electrical connection is present. v dd q supply dq power supply : +2.5v 0.2v. v ss q supply dq ground. v dd supply power supply : +2.5v 0.2v (device specific). v ss supply ground. v ref input sstl_2 reference voltage. - 7 - 256mb ddr sdram rev. 0.4 may. 2002 command truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we ba 0,1 a 10 /ap a 11, a 12 a 9 ~ a 0 note register extended mrs h x l l l l op code 1, 2 register mode register set h x l l l l op code 1, 2 refresh auto refresh h h l l l h x 3 self refresh entry l 3 exit l h l h h h x 3 h x x x 3 bank active & row address h x l l h h v row address read & column address auto precharge disable h x l h l h v l column address 4 auto precharge enable h 4 write & column address auto precharge disable h x l h l l v l column address 4 auto precharge enable h 4, 6 burst stop h x l h h l x 7 precharge bank selection h x l l h l v l x all banks x h 5 active power down entry h l h x x x x l v v v exit l h x x x x precharge power down mode entry h l h x x x x l h h h exit l h h x x x l v v v dm h x x 8 no op eration (nop) : not defined h x h x x x x 9 l h h h 9 1. op code : operand code. a 0 ~ a 12 & ba 0 ~ ba 1 : program keys. (@emrs/mrs) 2.emrs/ mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank b is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. 5. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data-in are masked at the both edges (write dm latency is 0). 9. this combination is not defined for any function, which means "no operation(nop)" in ddr sdram. - 8 - k4h560438d ddr sdram rev. 0.4 may. 2002 16m x 4bit x 4 banks double data rate sdram absolute maximum rating parameter symbol value unit voltage on any pin relative to vss vin, vout -0.5 ~ 3.6 v voltage on vdd & vddq supply relative to vss vdd, vddq -1.0 ~ 3.6 v storage temperature tstg -55 ~ +150 c power dissipation pd 1.5 w short circuit current ios 50 ma note : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommend operation condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability dc operating conditions the k4h560438d is 268,435,456 bits of double data rate synchronous dram organized as 4 x 16,777,216 words by 4 bits, fabricated with samsung s high performance cmos technology. synchronous features with data strobe allow extremely high performance up to 333mb/s per pin. i/o transactions are possible on both edges of dqs. range of operating frequencies, programmable burst length a nd programmable latencies allow the device to be useful for a variety of high performance memory system applications. general description recommended operating conditions(voltage referenced to v ss =0v, t a = 0 to 70 c) parameter symbol min max unit note supply voltage(for device with a nominal v dd of 2.5v) v dd 2.3 2.7 i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref vddq/2-50mv vddq/2+50mv v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v 2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v 4 input logic low voltage v il (dc) -0.3 v ref -0.15 v 4 input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.3 v ddq +0.6 v 3 input crossing point voltage, ck and ck inputs v ix (dc) 1.15 1.35 v 5 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current(normal strengh driver) ;v out = v tt + 0.84v i oh -16.8 ma output high current(normal strengh driver) ;v out = v tt - 0.84v i ol 16.8 ma output high current(half strengh driver) ;v out = v tt + 0.45v i oh -9 ma output high current(half strengh driver) ;v out = v tt - 0.45v i ol 9 ma - 9 - k4h560438d ddr sdram rev. 0.4 may. 2002 notes 1. includes 25mv margin for dc offset on v ref , and a combined total of 50mv margin for all ac noise and dc offset on v ref , bandwidth limited to 20mhz. the dram must accommodate dram current spikes on v ref and internal dram noise coupled to v ref , both of which may result in v ref noise. v ref should be de-coupled with an inductance of 3nh. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. the ac and dc input specifications are relative to a vref envelop that has been bandwidth limited to 200mhz. 5. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. ddr sdram idd spec table ac operating conditions parameter/condition symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals vih(ac) vref + 0.31 v 3 input low (logic 0) voltage, dq, dqs and dm signals. vil(ac) vref - 0.31 v 3 input differential voltage, ck and ck inputs vid(ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs vix(ac) 0.5*vddq-0.2 0.5*vddq+0.2 v 2 note 1. vid is the magnitude of the difference between the input level on ck and the input on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. 3. these parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu lation. the ac and dc input specificatims are refation to a vref envelope that has been bandwidth limited 20mhz. (v dd =2.7v, t = 10 c ) parameter specification address & control pins data pins maximum peak amplitude allowed for overshoot 1.6 v 1.2v maximum peak amplitude allowed for undershoot 1.6 v 1.2v the area between the overshoot signal and vdd must be less than or equal to 4.5 v-ns 2.5 v-ns the area between the undershoot signal and gnd must be less than or equal to 4.5 v-ns 2.5 v-ns overshoot/undershoot specification symbol 64mx4 unit notes k4h560438d-tc/lb3 (ddr333) k4h560438d-tc/la2, b0 (ddr266a/b) k4h560438d-tc/la0 (ddr200) idd0 90 80 75 ma idd1 110 100 90 ma idd2p 3 3 3 ma idd2f 25 20 18 ma idd2q 20 18 16 ma idd3p 35 30 25 ma idd3n 55 45 40 ma idd4r 150 120 100 ma idd4w 160 135 110 ma idd5 180 165 150 ma idd6 normal 3 3 3 ma low power 1.5 1.5 1.5 ma optional idd7a 290 250 220 ma - 10 - k4h560438d ddr sdram rev. 0.4 may. 2002 ac timming parameters & specifications parameter symbol -tc/lb3 (ddr333) -tc/la2 (ddr266a) -tc/lb0 (ddr266b) -tc/la0 (ddr200) unit note min max min max min max min max row cycle time trc 60 65 65 70 ns refresh row cycle time trfc 72 75 75 80 ns row active time tras 42 70k 45 120k 45 120k 48 120k ns ras to cas delay trcd 18 20 20 20 ns row precharge time trp 18 20 20 20 ns row active to row active delay trrd 12 15 15 15 ns write recovery time twr 15 15 15 15 ns last data in to read command twtr 1 1 1 1 tck col. address to col. address delay tccd 1 1 1 1 tck clock cycle time cl=2.0 tck 7.5 12 7.5 12 10 12 10 12 ns 5 cl=2.5 6 12 7.5 12 7.5 12 ns 5 clock high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ ck tdqsck -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns output data access time from ck/ ck tac -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns data strobe edge to ouput data edge tdqsq - 0.45 - 0.5 - 0.5 - 0.6 ns 5 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs-in setup time twpres 0 0 0 0 ns 2 dqs-in hold time twpre 0.25 0.25 0.25 0.25 tck dqs falling edge to ck rising-setup time tdss 0.2 0.2 0.2 0.2 tck dqs falling edge from ck rising-hold time tdsh 0.2 0.2 0.2 0.2 tck dqs-in high level width tdqsh 0.35 0.35 0.35 0.35 tck dqs-in low level width tdqsl 0.35 0.35 0.35 0.35 tck dqs-in cycle time tdsc 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck address and control input setup time(fast) tis 0.75 0.9 0.9 1.1 ns 6 address and control input hold time(fast) tih 0.75 0.9 0.9 1.1 ns 6 address and control input setup time(slow) tis 0.8 1.0 1.0 1.1 ns 6 address and control input hold time(slow) tih 0.8 1.0 1.0 1.1 ns 6 data-out high impedence time from ck/ ck thz -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns data-out low impedence time from ck/ ck tlz -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns input slew rate(for input only pins) tsl(i) 0.5 0.5 0.5 0.5 v/ns 6 input slew rate(for i/o pins) tsl(io) 0.5 0.5 0.5 0.5 v/ns 7 output slew rate(x4,x8) tsl(o) 1.0 4.5 1.0 4.5 1.0 4.5 1.0 4.5 v/ns 10 output slew rate matching ratio(rise to fall) tslmr 0.67 1.5 0.67 1.5 0.67 1.5 0.67 1.5 - 11 - k4h560438d ddr sdram rev. 0.4 may. 2002 1. maximum burst refresh cycle : 8 2. the specific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on tdqss. 3. the maximum limit for this parameter is not a device limit. the device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. a write command can be applied with t rcd satisfied after this command. 5. for registered dimms, t cl and t ch are 3 45% of the period including both the half period jitter (t jit(hp) ) of the pll and the half period jitter due to crosstalk (t jit (crosstalk) ) on the dimm. 6. input setup/hold slew rate derating this derating table is used to increase t is /t ih in the case where the input slew rate is below 0.5v/ns. input setup/hold slew rate based on the lesser of ac-ac slew rate and dc-dc slew rate. 7. i/o setup/hold slew rate derating this derating table is used to increase t ds /t dh in the case where the i/o slew rate is below 0.5v/ns. i/o setup/hold slew rate based on the lesser of ac-ac slew rate and dc-dc slew rate. parameter symbol -tc/lb3 (ddr333) -tc/la2 (ddr266a) -tc/lb0 (ddr266b) -tc/la0 (ddr200) unit note min max min max min max min max mode register set cycle time tmrd 12 15 15 16 ns dq & dm setup time to dqs tds 0.45 0.5 0.5 0.6 ns 7,8,9 dq & dm hold time to dqs tdh 0.45 0.5 0.5 0.6 ns 7,8,9 control & address input pulse width tipw 2.2 2.2 2.2 2.5 ns dq & dm input pulse width tdipw 1.75 1.75 1.75 2 ns power down exit time tpdex 6 7.5 7.5 10 ns exit self refresh to non-read command txsnr 75 75 75 80 ns 4 exit self refresh to read command txsrd 200 200 200 200 tck refresh interval time trefi 7.8 7.8 7.8 7.8 us 1 output dqs valid window tqh thp -tqhs - thp -tqhs - thp -tqhs - thp -tqhs - ns 5 clock half period thp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - ns data hold skew factor tqhs 0.55 0.75 0.75 0.8 ns dqs write postamble time twpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck 3 active to read with auto precharge command trap 18 20 20 20 autoprecharge write recovery + precharge time tdal (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) tck 11 input setup/hold slew rate d tis d tih (v/ns) (ps) (ps) 0.5 0 0 0.4 +50 +50 0.3 +100 +100 i/o setup/hold slew rate d tds d tdh (v/ns) (ps) (ps) 0.5 0 0 0.4 +75 +75 0.3 +150 +150 - 12 - k4h560438d ddr sdram rev. 0.4 may. 2002 8. i/o setup/hold plateau derating this derating table is used to increase tds/tdh in the case where the input level is flat below vref 310mv for a duration of up to 2ns. 9. i/o delta rise/fall rate(1/slew-rate) derating this derating table is used to increase t ds /t dh in the case where the dq and dqs slew rates differ. the delta rise/fall rate is calated as 1/slewrate1-1/slewrate2. for example, if slew rate 1 = 5v/ns and slew rate 2 =.4v/ns then the delta rise/fall rate =-0/5ns/v. input s/h slew rate based on larger of ac-ac delta rise/fall rate and dc-dc delta rise/fall rate. 10. this parameter is fir system simulation purpose. it is guranteed by design. 11. for each of the terms, if not already an integer, round to the next highest integer. tck is actual to the system clock cyc le time. i/o input level d tds d tdh (mv) (ps) (ps) 280 +50 +50 delta rise/fall rate d tds d tdh (ns/v) (ps) (ps) 0 0 0 0.25 +50 +50 0.5 +100 +100 the following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0 v/ns. ck slew rate (single ended) d tih/tis (ps) d tdss/tdsh (ps) d tac/tdqsck (ps) d tlz(min) (ps) d thz(max) (ps) 1.0v/ns 0 0 0 0 0 0.75v/ns +50 +50 +50 -50 +50 0.5v/ns +100 +100 +100 -100 +100 - 13 - k4h560438d ddr sdram rev. 0.4 may. 2002 ac operating test conditions input/output capacitance (vdd=2.5, vddq=2.5v, ta= 25 c, f=1mhz) parameter symbol min max delta cap(max) unit input capacitance (a0 ~ a12, ba0 ~ ba1, cke, cs , ras , cas , we ) cin1 2 3.0 0.5 pf input capacitance( ck, ck ) cin2 2 3.0 0.25 pf data & dqs input/output capacitance cout 4.0 5.0 0.5 pf input capacitance(dm) cin3 4.0 5.0 pf output load circuit (sstl_2) output z0=50 w c load =30pf v ref =0.5*v ddq r t =50 w v tt =0.5*v ddq (v dd =2.5v, v ddq =2.5v, t a = 0 to 70 c) parameter value unit note input reference voltage for clock 0.5 * v ddq v input signal maximum peak swing 1.5 v input signal minimum slew rate (for imput only) 0.5 v/ns input slew rate (i/o pins) 0.5 v/ns input levels(v ih /v il ) v ref +0.31/v ref -0.31 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see load circuit - 14 - k4h560838d ddr sdram rev. 0.4 may. 2002 8m x 8bit x 4 banks double data rate sdram absolute maximum rating parameter symbol value unit voltage on any pin relative to vss vin, vout -0.5 ~ 3.6 v voltage on vdd & vddq supply relative to vss vdd, vddq -1.0 ~ 3.6 v storage temperature tstg -55 ~ +150 c power dissipation pd 1.5 w short circuit current ios 50 ma note : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommend operation condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability dc operating conditions the k4h560838d is 268,435,456 bits of double data rate synchronous dram organized as 4 x 8,388,608 words by 8 bits, fabricated with samsung s high performance cmos technology. synchronous features with data strobe allow extremely high performance up to 333mb/s per pin. i/o transactions are possible on both edges of dqs. range of operating frequencies, programmable burst lengt h and programmable latencies allow the device to be useful for a variety of high performance memory system applications. general description recommended operating conditions(voltage referenced to v ss =0v, t a = 0 to 70 c) parameter symbol min max unit note supply voltage(for device with a nominal v dd of 2.5v) v dd 2.3 2.7 i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref vddq/2-50mv vddq/2+50mv v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v 2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v 4 input logic low voltage v il (dc) -0.3 v ref -0.15 v 4 input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.3 v ddq +0.6 v 3 input crossing point voltage, ck and ck inputs v ix (dc) 1.15 1.35 v 5 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current(normal strengh driver) ;v out = v tt + 0.84v i oh -16.8 ma output high current(normal strengh driver) ;v out = v tt - 0.84v i ol 16.8 ma output high current(half strengh driver) ;v out = v tt + 0.45v i oh -9 ma output high current(half strengh driver) ;v out = v tt - 0.45v i ol 9 ma - 15 - k4h560838d ddr sdram rev. 0.4 may. 2002 notes 1. includes 25mv margin for dc offset on v ref , and a combined total of 50mv margin for all ac noise and dc offset on v ref , bandwidth limited to 20mhz. the dram must accommodate dram current spikes on v ref and internal dram noise coupled to v ref , both of which may result in v ref noise. v ref should be de-coupled with an inductance of 3nh. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. the ac and dc input specifications are relative to a vref envelop that has been bandwidth limited to 200mhz. 5. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. ddr sdram idd spec table ac operating conditions parameter/condition symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals vih(ac) vref + 0.31 v 3 input low (logic 0) voltage, dq, dqs and dm signals. vil(ac) vref - 0.31 v 3 input differential voltage, ck and ck inputs vid(ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs vix(ac) 0.5*vddq-0.2 0.5*vddq+0.2 v 2 note 1. vid is the magnitude of the difference between the input level on ck and the input on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. 3. these parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu lation. the ac and dc input specificatims are refation to a vref envelope that has been bandwidth limited 20mhz. (v dd =2.7v, t = 10 c ) parameter specification address & control pins data pins maximum peak amplitude allowed for overshoot 1.6 v 1.2v maximum peak amplitude allowed for undershoot 1.6 v 1.2v the area between the overshoot signal and vdd must be less than or equal to 4.5 v-ns 2.5 v-ns the area between the undershoot signal and gnd must be less than or equal to 4.5 v-ns 2.5 v-ns overshoot/undershoot specification symbol 32mx8 unit notes k4h560838d-tc/lb3 (ddr333) k4h560838d-tc/la2, cb0 (ddr266a/b) k4h560838d-tc/la0 (ddr200) idd0 90 80 75 ma idd1 120 110 100 ma idd2p 3 3 3 ma idd2f 25 20 18 ma idd2q 20 18 16 ma idd3p 35 30 25 ma idd3n 55 45 40 ma idd4r 170 140 120 ma idd4w 170 140 115 ma idd5 180 165 150 ma idd6 normal 3 3 3 ma low power 1.5 1.5 1.5 ma optional idd7a 325 280 235 ma - 16 - k4h560838d ddr sdram rev. 0.4 may. 2002 ac timming parameters & specifications parameter symbol -tc/lb3 (ddr333) -tc/la2 (ddr266a) -tc/lb0 (ddr266b) -tc/la0 (ddr200) unit note min max min max min max min max row cycle time trc 60 65 65 70 ns refresh row cycle time trfc 72 75 75 80 ns row active time tras 42 70k 45 120k 45 120k 48 120k ns ras to cas delay trcd 18 20 20 20 ns row precharge time trp 18 20 20 20 ns row active to row active delay trrd 12 15 15 15 ns write recovery time twr 15 15 15 15 ns last data in to read command twtr 1 1 1 1 tck col. address to col. address delay tccd 1 1 1 1 tck clock cycle time cl=2.0 tck 7.5 12 7.5 12 10 12 10 12 ns 5 cl=2.5 6 12 7.5 12 7.5 12 ns 5 clock high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ ck tdqsck -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns output data access time from ck/ ck tac -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns data strobe edge to ouput data edge tdqsq - 0.45 - 0.5 - 0.5 - 0.6 ns 5 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs-in setup time twpres 0 0 0 0 ns 2 dqs-in hold time twpre 0.25 0.25 0.25 0.25 tck dqs falling edge to ck rising-setup time tdss 0.2 0.2 0.2 0.2 tck dqs falling edge from ck rising-hold time tdsh 0.2 0.2 0.2 0.2 tck dqs-in high level width tdqsh 0.35 0.35 0.35 0.35 tck dqs-in low level width tdqsl 0.35 0.35 0.35 0.35 tck dqs-in cycle time tdsc 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck address and control input setup time(fast) tis 0.75 0.9 0.9 1.1 ns 6 address and control input hold time(fast) tih 0.75 0.9 0.9 1.1 ns 6 address and control input setup time(slow) tis 0.8 1.0 1.0 1.1 ns 6 address and control input hold time(slow) tih 0.8 1.0 1.0 1.1 ns 6 data-out high impedence time from ck/ ck thz -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns data-out low impedence time from ck/ ck tlz -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns input slew rate(for input only pins) tsl(i) 0.5 0.5 0.5 0.5 v/ns 6 input slew rate(for i/o pins) tsl(io) 0.5 0.5 0.5 0.5 v/ns 7 output slew rate(x4,x8) tsl(o) 1.0 4.5 1.0 4.5 1.0 4.5 1.0 4.5 v/ns 10 output slew rate matching ratio(rise to fall) tslmr 0.67 1.5 0.67 1.5 0.67 1.5 0.67 1.5 - 17 - k4h560838d ddr sdram rev. 0.4 may. 2002 1. maximum burst refresh cycle : 8 2. the specific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on tdqss. 3. the maximum limit for this parameter is not a device limit. the device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. a write command can be applied with t rcd satisfied after this command. 5. for registered dimms, t cl and t ch are 3 45% of the period including both the half period jitter (t jit(hp) ) of the pll and the half period jitter due to crosstalk (t jit (crosstalk) ) on the dimm. 6. input setup/hold slew rate derating this derating table is used to increase t is /t ih in the case where the input slew rate is below 0.5v/ns. input setup/hold slew rate based on the lesser of ac-ac slew rate and dc-dc slew rate. 7. i/o setup/hold slew rate derating this derating table is used to increase t ds /t dh in the case where the i/o slew rate is below 0.5v/ns. i/o setup/hold slew rate based on the lesser of ac-ac slew rate and dc-dc slew rate. parameter symbol -tc/lb3 (ddr333) -tc/la2 (ddr266a) -tc/lb0 (ddr266b) -tc/la0 (ddr200) unit note min max min max min max min max mode register set cycle time tmrd 12 15 15 16 ns dq & dm setup time to dqs tds 0.45 0.5 0.5 0.6 ns 7,8,9 dq & dm hold time to dqs tdh 0.45 0.5 0.5 0.6 ns 7,8,9 control & address input pulse width tipw 2.2 2.2 2.2 2.5 ns dq & dm input pulse width tdipw 1.75 1.75 1.75 2 ns power down exit time tpdex 6 7.5 7.5 10 ns exit self refresh to non-read command txsnr 75 75 75 80 ns 4 exit self refresh to read command txsrd 200 200 200 200 tck refresh interval time trefi 7.8 7.8 7.8 7.8 us 1 output dqs valid window tqh thp -tqhs - thp -tqhs - thp -tqhs - thp -tqhs - ns 5 clock half period thp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - ns data hold skew factor tqhs 0.55 0.75 0.75 0.8 ns dqs write postamble time twpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck 3 active to read with auto precharge command trap 18 20 20 20 autoprecharge write recovery + precharge time tdal (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) tck 11 input setup/hold slew rate d tis d tih (v/ns) (ps) (ps) 0.5 0 0 0.4 +50 +50 0.3 +100 +100 i/o setup/hold slew rate d tds d tdh (v/ns) (ps) (ps) 0.5 0 0 0.4 +75 +75 0.3 +150 +150 - 18 - k4h560838d ddr sdram rev. 0.4 may. 2002 8. i/o setup/hold plateau derating this derating table is used to increase tds/tdh in the case where the input level is flat below vref 310mv for a duration of up to 2ns. 9. i/o delta rise/fall rate(1/slew-rate) derating this derating table is used to increase t ds /t dh in the case where the dq and dqs slew rates differ. the delta rise/fall rate is calated as 1/slewrate1-1/slewrate2. for example, if slew rate 1 = 5v/ns and slew rate 2 =.4v/ns then the delta rise/fall rate =-0/5ns/v. input s/h slew rate based on larger of ac-ac delta rise/fall rate and dc-dc delta rise/fall rate. 10. this parameter is fir system simulation purpose. it is guranteed by design. 11. for each of the terms, if not already an integer, round to the next highest integer. tck is actual to the system clock cyc le time. i/o input level d tds d tdh (mv) (ps) (ps) 280 +50 +50 delta rise/fall rate d tds d tdh (ns/v) (ps) (ps) 0 0 0 0.25 +50 +50 0.5 +100 +100 the following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0 v/ns. ck slew rate (single ended) d tih/tis (ps) d tdss/tdsh (ps) d tac/tdqsck (ps) d tlz(min) (ps) d thz(max) (ps) 1.0v/ns 0 0 0 0 0 0.75v/ns +50 +50 +50 -50 +50 0.5v/ns +100 +100 +100 -100 +100 - 19 - k4h560838d ddr sdram rev. 0.4 may. 2002 ac operating test conditions input/output capacitance (vdd=2.5, vddq=2.5v, ta= 25 c, f=1mhz) parameter symbol min max delta cap(max) unit input capacitance (a0 ~ a12, ba0 ~ ba1, cke, cs , ras , cas , we ) cin1 2 3.0 0.5 pf input capacitance( ck, ck ) cin2 2 3.0 0.25 pf data & dqs input/output capacitance cout 4.0 5.0 0.5 pf input capacitance(dm) cin3 4.0 5.0 pf output load circuit (sstl_2) output z0=50 w c load =30pf v ref =0.5*v ddq r t =50 w v tt =0.5*v ddq (v dd =2.5v, v ddq =2.5v, t a = 0 to 70 c) parameter value unit note input reference voltage for clock 0.5 * v ddq v input signal maximum peak swing 1.5 v input signal minimum slew rate (for imput only) 0.5 v/ns input slew rate (i/o pins) 0.5 v/ns input levels(v ih /v il ) v ref +0.31/v ref -0.31 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see load circuit - 20 - k4h561638d ddr sdram rev. 0.4 may. 2002 4m x 16bit x 4 banks double data rate sdram the k4h561638d is 268435456 bits of double data rate synchronous dram organized as 4 x 4,194,304 words by 16 bits, fabricated with samsung s high performance cmos technology. synchronous features with data strobe allow extremely high performance up to 333mb/s per pin. i/o transactions are possible on both edges of dqs. range of operating frequencies, programmable burst length a nd programmable latencies allow the device to be useful for a variety of high performance memory system applications. general description absolute maximum rating parameter symbol value unit voltage on any pin relative to vss vin, vout -0.5 ~ 3.6 v voltage on vdd & vddq supply relative to vss vdd, vddq -1.0 ~ 3.6 v storage temperature tstg -55 ~ +150 c power dissipation pd 1.5 w short circuit current ios 50 ma note : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommend operation condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability dc operating conditions recommended operating conditions(voltage referenced to v ss =0v, t a = 0 to 70 c) parameter symbol min max unit note supply voltage(for device with a nominal v dd of 2.5v) v dd 2.3 2.7 i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref vddq/2-50mv vddq/2+50mv v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v 2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v 4 input logic low voltage v il (dc) -0.3 v ref -0.15 v 4 input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.3 v ddq +0.6 v 3 input crossing point voltage, ck and ck inputs v ix (dc) 1.15 1.35 v 5 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current(normal strengh driver) ;v out = v tt + 0.84v i oh -16.8 ma output high current(normal strengh driver) ;v out = v tt - 0.84v i ol 16.8 ma output high current(half strengh driver) ;v out = v tt + 0.45v i oh -9 ma output high current(half strengh driver) ;v out = v tt - 0.45v i ol 9 ma - 21 - k4h561638d ddr sdram rev. 0.4 may. 2002 notes 1. includes 25mv margin for dc offset on v ref , and a combined total of 50mv margin for all ac noise and dc offset on v ref , bandwidth limited to 20mhz. the dram must accommodate dram current spikes on v ref and internal dram noise coupled to v ref , both of which may result in v ref noise. v ref should be de-coupled with an inductance of 3nh. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. the ac and dc input specifications are relative to a vref envelop that has been bandwidth limited to 200mhz. 5. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. ddr sdram idd spec table (v dd =2.7v, t = 10 c ) ac operating conditions parameter/condition symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals vih(ac) vref + 0.31 v 3 input low (logic 0) voltage, dq, dqs and dm signals. vil(ac) vref - 0.31 v 3 input differential voltage, ck and ck inputs vid(ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs vix(ac) 0.5*vddq-0.2 0.5*vddq+0.2 v 2 note 1. vid is the magnitude of the difference between the input level on ck and the input on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. 3. these parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simu lation. the ac and dc input specificatims are refation to a vref envelope that has been bandwidth limited 20mhz. parameter specification address & control pins data pins maximum peak amplitude allowed for overshoot 1.6 v 1.2v maximum peak amplitude allowed for undershoot 1.6 v 1.2v the area between the overshoot signal and vdd must be less than or equal to 4.5 v-ns 2.5 v-ns the area between the undershoot signal and gnd must be less than or equal to 4.5 v-ns 2.5 v-ns overshoot/undershoot specification symbol 16mx16 unit notes k4h561638d-tc/lb3 (ddr333) k4h561638d-tc/la2, b0 (ddr266a/b) k4h561638d-tc/la0 (ddr200) idd0 90 80 75 ma idd1 125 115 105 ma idd2p 3 3 3 ma idd2f 25 20 18 ma idd2q 20 18 16 ma idd3p 35 30 25 ma idd3n 55 45 40 ma idd4r 200 170 150 ma idd4w 190 155 130 ma idd5 180 165 150 ma idd6 normal 3 3 3 ma low power 1.5 1.5 1.5 ma optional idd7a 350 300 260 ma - 22 - k4h561638d ddr sdram rev. 0.4 may. 2002 ac timming parameters & specifications parameter symbol -tc/lb3 (ddr333) -tc/la2 (ddr266a) -tc/lb0 (ddr266b) -tc/la0 (ddr200) unit note min max min max min max min max row cycle time trc 60 65 65 70 ns refresh row cycle time trfc 72 75 75 80 ns row active time tras 42 70k 45 120k 45 120k 48 120k ns ras to cas delay trcd 18 20 20 20 ns row precharge time trp 18 20 20 20 ns row active to row active delay trrd 12 15 15 15 ns write recovery time twr 15 15 15 15 ns last data in to read command twtr 1 1 1 1 tck col. address to col. address delay tccd 1 1 1 1 tck clock cycle time cl=2.0 tck 7.5 12 7.5 12 10 12 10 12 ns 5 cl=2.5 6 12 7.5 12 7.5 12 ns 5 clock high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ ck tdqsck -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns output data access time from ck/ ck tac -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns data strobe edge to ouput data edge tdqsq - 0.45 - 0.5 - 0.5 - 0.6 ns 5 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs-in setup time twpres 0 0 0 0 ns 2 dqs-in hold time twpre 0.25 0.25 0.25 0.25 tck dqs falling edge to ck rising-setup time tdss 0.2 0.2 0.2 0.2 tck dqs falling edge from ck rising-hold time tdsh 0.2 0.2 0.2 0.2 tck dqs-in high level width tdqsh 0.35 0.35 0.35 0.35 tck dqs-in low level width tdqsl 0.35 0.35 0.35 0.35 tck dqs-in cycle time tdsc 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck address and control input setup time(fast) tis 0.75 0.9 0.9 1.1 ns 6 address and control input hold time(fast) tih 0.75 0.9 0.9 1.1 ns 6 address and control input setup time(slow) tis 0.8 1.0 1.0 1.1 ns 6 address and control input hold time(slow) tih 0.8 1.0 1.0 1.1 ns 6 data-out high impedence time from ck/ ck thz -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns data-out low impedence time from ck/ ck tlz -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns input slew rate(for input only pins) tsl(i) 0.5 0.5 0.5 0.5 v/ns 6 input slew rate(for i/o pins) tsl(io) 0.5 0.5 0.5 0.5 v/ns 7 output slew rate(x4,x8) tsl(o) 1.0 4.5 1.0 4.5 1.0 4.5 1.0 4.5 v/ns 10 output slew rate matching ratio(rise to fall) tslmr 0.67 1.5 0.67 1.5 0.67 1.5 0.67 1.5 - 23 - k4h561638d ddr sdram rev. 0.4 may. 2002 1. maximum burst refresh cycle : 8 2. the specific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on tdqss. 3. the maximum limit for this parameter is not a device limit. the device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. a write command can be applied with t rcd satisfied after this command. 5. for registered dimms, t cl and t ch are 3 45% of the period including both the half period jitter (t jit(hp) ) of the pll and the half period jitter due to crosstalk (t jit (crosstalk) ) on the dimm. 6. input setup/hold slew rate derating this derating table is used to increase t is /t ih in the case where the input slew rate is below 0.5v/ns. input setup/hold slew rate based on the lesser of ac-ac slew rate and dc-dc slew rate. 7. i/o setup/hold slew rate derating this derating table is used to increase t ds /t dh in the case where the i/o slew rate is below 0.5v/ns. i/o setup/hold slew rate based on the lesser of ac-ac slew rate and dc-dc slew rate. parameter symbol -tc/lb3 (ddr333) -tc/la2 (ddr266a) -tc/lb0 (ddr266b) -tc/la0 (ddr200) unit note min max min max min max min max mode register set cycle time tmrd 12 15 15 16 ns dq & dm setup time to dqs tds 0.45 0.5 0.5 0.6 ns 7,8,9 dq & dm hold time to dqs tdh 0.45 0.5 0.5 0.6 ns 7,8,9 control & address input pulse width tipw 2.2 2.2 2.2 2.5 ns dq & dm input pulse width tdipw 1.75 1.75 1.75 2 ns power down exit time tpdex 6 7.5 7.5 10 ns exit self refresh to non-read command txsnr 75 75 75 80 ns 4 exit self refresh to read command txsrd 200 200 200 200 tck refresh interval time trefi 7.8 7.8 7.8 7.8 us 1 output dqs valid window tqh thp -tqhs - thp -tqhs - thp -tqhs - thp -tqhs - ns 5 clock half period thp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - ns data hold skew factor tqhs 0.55 0.75 0.75 0.8 ns dqs write postamble time twpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck 3 active to read with auto precharge command trap 18 20 20 20 autoprecharge write recovery + precharge time tdal (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) tck 11 input setup/hold slew rate d tis d tih (v/ns) (ps) (ps) 0.5 0 0 0.4 +50 +50 0.3 +100 +100 i/o setup/hold slew rate d tds d tdh (v/ns) (ps) (ps) 0.5 0 0 0.4 +75 +75 0.3 +150 +150 - 24 - k4h561638d ddr sdram rev. 0.4 may. 2002 8. i/o setup/hold plateau derating this derating table is used to increase tds/tdh in the case where the input level is flat below vref 310mv for a duration of up to 2ns. 9. i/o delta rise/fall rate(1/slew-rate) derating this derating table is used to increase t ds /t dh in the case where the dq and dqs slew rates differ. the delta rise/fall rate is calated as 1/slewrate1-1/slewrate2. for example, if slew rate 1 = 5v/ns and slew rate 2 =.4v/ns then the delta rise/fall rate =-0/5ns/v. input s/h slew rate based on larger of ac-ac delta rise/fall rate and dc-dc delta rise/fall rate. 10. this parameter is fir system simulation purpose. it is guranteed by design. 11. for each of the terms, if not already an integer, round to the next highest integer. tck is actual to the system clock cyc le time. i/o input level d tds d tdh (mv) (ps) (ps) 280 +50 +50 delta rise/fall rate d tds d tdh (ns/v) (ps) (ps) 0 0 0 0.25 +50 +50 0.5 +100 +100 the following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0 v/ns. ck slew rate (single ended) d tih/tis (ps) d tdss/tdsh (ps) d tac/tdqsck (ps) d tlz(min) (ps) d thz(max) (ps) 1.0v/ns 0 0 0 0 0 0.75v/ns +50 +50 +50 -50 +50 0.5v/ns +100 +100 +100 -100 +100 - 25 - k4h561638d ddr sdram rev. 0.4 may. 2002 ac operating test conditions input/output capacitance (vdd=2.5, vddq=2.5v, ta= 25 c, f=1mhz) parameter symbol min max delta cap(max) unit input capacitance (a0 ~ a12, ba0 ~ ba1, cke, cs , ras , cas , we ) cin1 2 3.0 0.5 pf input capacitance( ck, ck ) cin2 2 3.0 0.25 pf data & dqs input/output capacitance cout 4.0 5.0 0.5 pf input capacitance(dm) cin3 4.0 5.0 pf output load circuit (sstl_2) output z0=50 w c load =30pf v ref =0.5*v ddq r t =50 w v tt =0.5*v ddq (v dd =2.5v, v ddq =2.5v, t a = 0 to 70 c) parameter value unit note input reference voltage for clock 0.5 * v ddq v input signal maximum peak swing 1.5 v input signal minimum slew rate (for imput only) 0.5 v/ns input slew rate (i/o pins) 0.5 v/ns input levels(v ih /v il ) v ref +0.31/v ref -0.31 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see load circuit |
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